India is preparing to introduce a 9% deployment-linked incentive (DLI) for domestic semiconductor startups under the proposed Semicon 2.0 programme, aiming to reduce the high cost of manufacturing prototype chips and accelerate indigenous chip design. The incentive is designed to offset a key expense faced by early-stage chip companies when fabricating prototype semiconductors at commercial foundries, a process that can take more than a year and cost up to ₹2,000 crore.
According to India Semiconductor Mission (ISM) CEO Amitesh Sinha, the scheme will provide startups with a 9% deployment incentive, helping them absorb fabrication costs while encouraging the creation of homegrown semiconductor intellectual property (IP). The government expects the initiative to contribute to the development of India’s own chip patents over the next five years.
India Plans 9% Incentive for Chip Design Startups
The proposed measure forms part of the government’s broader effort to strengthen India’s semiconductor ecosystem under Semicon 2.0.
| Key Highlights | Details |
|---|---|
| Scheme | Semicon 2.0 (proposed) |
| Incentive | 9% deployment-linked incentive |
| Beneficiaries | Indian semiconductor design startups |
| Objective | Lower prototype chip fabrication costs |
| Long-term goal | Build indigenous chip IP and fabless companies |
| Implementing agency | India Semiconductor Mission (ISM) |
The incentive targets one of the biggest barriers for semiconductor startups—high fabrication costs and long waiting periods at overseas chip foundries.
Why the 9% Incentive Matters
Building prototype chips is expensive because startups typically lack the pricing advantages enjoyed by large global semiconductor firms.
Key reasons behind the incentive include:
- Reducing prototype fabrication costs.
- Supporting early-stage semiconductor startups.
- Encouraging indigenous chip innovation.
- Helping startups commercialize chip designs faster.
- Building India’s fabless semiconductor ecosystem.
- Promoting domestic semiconductor patents.
According to ISM, while large chip companies often receive fabrication discounts from commercial foundries, startups generally do not. The proposed incentive is intended to narrow that cost gap.
Beyond Financial Support
The government is also exploring measures to improve startup access to global fabrication capacity.
Potential initiatives include:
- Agreements with strategic overseas foundries.
- Faster access to fabrication slots.
- Collaboration with chip fabrication aggregators.
- Support through Belgium-based IMEC.
- Future access to domestic fabrication facilities, including Tata Electronics’ planned Dholera fab.
- Continued technical validation through C-DAC.
These efforts aim to reduce both the cost and the time required for Indian startups to bring new chip designs to market.
Scheme Snapshot
| Metric | Details |
|---|---|
| Proposed incentive | 9% deployment-linked incentive |
| Focus | Semiconductor design startups |
| Programme | Semicon 2.0 |
| Expected outcome | More indigenous chip designs |
| Long-term vision | Create globally competitive fabless companies |
| Government target | Strengthen India’s semiconductor ecosystem |
The proposal complements the Union Cabinet’s recently approved ₹1.27 lakh crore second phase of the India Semiconductor Mission, which seeks to expand domestic semiconductor manufacturing, design, packaging, and supply chains.
Impact on India’s Semiconductor Industry
If implemented, the incentive could significantly improve the economics of chip innovation in India.
Potential benefits include:
- Higher investment in semiconductor R&D.
- Faster commercialization of chip designs.
- Growth of fabless semiconductor startups.
- Increased domestic intellectual property creation.
- Reduced dependence on imported chip technologies.
- Stronger integration into global semiconductor supply chains.
The initiative also supports India’s ambition to become a global hub for semiconductor design alongside manufacturing.
Challenges Ahead
Despite the proposed support, several hurdles remain.
These include:
- Limited access to commercial fabrication capacity.
- Long prototype manufacturing timelines.
- High research and development costs.
- Shortage of advanced semiconductor talent.
- Dependence on overseas foundries until domestic fabs become operational.
- Intense global competition in semiconductor design.
Addressing these challenges will require continued investment in infrastructure, skills, research, and international partnerships.
Outlook
The proposed 9% deployment-linked incentive represents an important shift in India’s semiconductor strategy by focusing not only on manufacturing but also on nurturing domestic chip design startups. Lowering the financial burden of prototype fabrication could enable more startups to transform innovative designs into commercial products while building valuable intellectual property within the country.
Combined with investments in fabrication plants, packaging facilities, and design-linked incentives, Semicon 2.0 aims to create a more complete semiconductor ecosystem capable of supporting India’s long-term ambitions in electronics manufacturing, artificial intelligence, automotive electronics, telecommunications, and defense technologies.
What It Means for India’s Technology Sector
The proposed incentive signals a broader policy shift toward fostering homegrown semiconductor innovation rather than relying solely on attracting foreign manufacturers. By reducing barriers for chip design startups, the government hopes to create globally competitive Indian semiconductor companies with proprietary intellectual property.
For India’s technology ecosystem, the move could stimulate innovation across AI, automotive, consumer electronics, industrial automation, and telecommunications while strengthening the country’s position in the global semiconductor value chain.
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